I am a retired engineer. I started with Motorola as a CMOS design engineer.
No synthesis at this time, all schematics on paper with netlists done by hand to be simulated by Logcap and then Silos or MCspice the Motorola Spice for analog simulations. Layouts were checked with rulers before Maskap arrives with LVS and DRC checks. Fract plots from Calma were checked visually to verify that all polygones were present especially the customer options and the memory programmation. Then IMB was abandonned with the rise of the workstations. We got Apollo workstations with Mentor software. Schematics were entered in Neted and we could get gate netlists from schematics. Layout were entered in Chipgraph outputing GDSII layout data base. Documentation was on Doc and then Framemaker. We then got Verilog gate netlists for Cadence VerilogXL and Verifault for fault simulations. Working on new projects, we had to switch unfortunatelly to Caeco software for schematics and layout. Then started the area of synthesis, schematics were abandonned and description were done in Verilog. Synthesis from Verilog RTL to gate was done with Synopsys Design Compiler. Co-simulation Verilog with Epic Timemill started , power estimation started with Epic Powermill. Tools for floorplanning were used. Checkmate and Calibre were used for DRC and LVS verification and probably Dracula. We bought an HP82000 tester to check physical circuits. Then came equivalence tools like Formality to check equivalency between behavioral rtl netlist, synthetized gate netlists with approximated parasitic and final place and route netlists with parasitics. Timing paths were analysed with PrimeTime with the painfull setting of clocks and exceptions. Joining a startup, documentation was done on Openoffice then Libreoffice then Microsoftoffice. To get better package price we changed for VCS logic simulator. We then got clock domain crossing tools because the number of clocks was increasing and we used queta CDC. The test methodoly changed with the rise of the UVM object methodology. Then I join a compagny working with VHDL and using Modelsim simulators. I have not mentionned the tools to keep track of all the revisions and problems of each modules composing a SOC, like Pegasus, bugzilla, redmine, the tools to keep track of the chip requirements from the original spec to the test patterns covering those requirements. Oh and I did not talk yet about the different revision control systems ClearCase, Svn and Git we had to use.
Better be a downtown doctor, the body is the body, nothing changes for them. If they make a mistake the customer doesn’t complain too much and they will never be fired as they are their own boss !